1. Field of the Invention
Embodiments of the invention provide a method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool.
2. Description of the Related Art
In the design and manufacture of very large scale integration (VLSI) semiconductor chips, two types of yield detractors in the manufacturing process are random defects and systematic defects. Random defects refer to electrical faults (e.g., opens and shorts) caused by foreign material or impurities. Systematic defects—also known as process-sensitive sites—constitute electrical faults that arise because of the inherent difficulty of repeatedly building certain structures in a given manufacturing technology.
Random defects are predicted using critical area. Critical area is a mathematical measure of the sensitivity of a VLSI layout to random defects. It is a function of the sizes of features and the spaces between features. There are several techniques for computing critical area (e.g., dot-throwing, geometric expansion, and Voronoi diagrams). Critical area models the sensitivity of a given manufacturing process to point defects. In the critical-area model, all shapes allowed in a technology are assumed to have equal defect sensitivity.
By contrast, systematic defects result because some structures are more difficult to manufacture than others. In a given process, certain geometrical configurations can be particularly susceptible to yield problems. For example: certain combinations of wide metal lines and narrow metal lines might interact in a certain way because of the polish stage and lead to electrical shorts and thus non-functional parts. In general, there is no simple way to measure the sensitivity of a design to systematic defects. One technique uses a design rule check (DRC) to look for certain configurations and then produce a raw count. While this technique provides a means of identifying sites that could cause yield issues, it does not allow yield to be predicted and does not provide a means to trade off options to lessen overall combined systematic and random yield sensitivity.
In addition there is a random component to systematic-defect analysis: a process-sensitive site is not guaranteed to cause an electrical fault but rather will cause a fault with some probability. An overall yield estimate for a semiconductor design therefore requires two separate analyses: critical area for random defects and quasi-DRC for systematic defects. Furthermore, the systematic-defect analysis should take into account the probabilistic nature of systematic defects. Presently, there is no good method for performing a unified analysis having these characteristics.